I’m an electrical engineer who has been pivoting into software and AI-focused work by building practical solutions for test automation and engineering workflows. For the past several years at AMD, I worked in FPGA design solutions verification and formed a small team to explore how LLMs can improve verification—especially through retrieval-augmented generation (RAG) and agentic coding patterns. I enjoy turning domain-specific rules and datasets into reliable software artifacts, using Python and modern LLM tooling to generate, review, and validate outputs. In parallel, I’ve continued re-skilling through hands-on RAG projects with LangChain and OpenAI APIs, and I’m excited to return to roles where I can combine strong engineering foundations with applied AI development to deliver measurable impact.

Alishba Kanwal

I’m an electrical engineer who has been pivoting into software and AI-focused work by building practical solutions for test automation and engineering workflows. For the past several years at AMD, I worked in FPGA design solutions verification and formed a small team to explore how LLMs can improve verification—especially through retrieval-augmented generation (RAG) and agentic coding patterns. I enjoy turning domain-specific rules and datasets into reliable software artifacts, using Python and modern LLM tooling to generate, review, and validate outputs. In parallel, I’ve continued re-skilling through hands-on RAG projects with LangChain and OpenAI APIs, and I’m excited to return to roles where I can combine strong engineering foundations with applied AI development to deliver measurable impact.

Available to hire

I’m an electrical engineer who has been pivoting into software and AI-focused work by building practical solutions for test automation and engineering workflows. For the past several years at AMD, I worked in FPGA design solutions verification and formed a small team to explore how LLMs can improve verification—especially through retrieval-augmented generation (RAG) and agentic coding patterns.

I enjoy turning domain-specific rules and datasets into reliable software artifacts, using Python and modern LLM tooling to generate, review, and validate outputs. In parallel, I’ve continued re-skilling through hands-on RAG projects with LangChain and OpenAI APIs, and I’m excited to return to roles where I can combine strong engineering foundations with applied AI development to deliver measurable impact.

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Language

English
Advanced
French
Intermediate
German
Intermediate
Urdu
Fluent
Panjabi, Punjabi
Advanced

Work Experience

Career Break
February 1, 2025 - Present
Parental care and personal development. During the career break, continued deepening knowledge from prior AI work at AMD by building projects involving Retrieval-Augmented Generation (RAG) with LangChain in Python and improving proficiency in agentic coding and AI-assisted software development.
Software Engineer at AMD
February 1, 2019 - February 1, 2025
Member of the DSV (Design Solutions Verification) team. Led an AI Initiative to investigate LLMs for improved test automation, including literature review on RAG, Python scripting for AI-driven use cases, and weekly team meetings. Example impact: used an LLM to translate an extensive FPGA clocking rules spreadsheet into structured Verilog unit tests and used the LLM to review manual test changes before publish; improved test coverage by 70%+ and reduced time to create tests from the ruleset. Continued maintaining and supporting verification workflows alongside AI experiments.
Technical Student at European Organisation for Nuclear Research (CERN)
February 1, 2017 - April 1, 2018
Developed C++ emulation model for a CMS Experiment data compression chip. Wrote VHDL firmware to establish an optical readout chain between the FC7 development board (Xilinx Kintex-7) and the GBTx optical link serializer/deserializer. Co-wrote VHDL module to interface FC7 with CERN middleware over an Ethernet wrapper. Built CI with Jenkins/Git to schedule overnight firmware builds.
Graduate Research Assistant at National University of Sciences and Technology (NUST) - CEFAR lab
August 1, 2015 - January 1, 2016
Researched and implemented partial reconfiguration techniques for Xilinx Series-6 FPGAs. Implemented an open-source LEON processor on Xilinx Virtex-6 as part of lab research.

Education

Master of Science in Electrical Engineering at National University of Sciences and Technology (NUST)
January 1, 2016 - September 1, 2018
Bachelor of Science in Electrical Engineering at University of Engineering and Technology (UET), Taxila
January 1, 2010 - June 1, 2014
High School Diploma (Edexcel GCE A Levels) at Saint Mary’s Catholic High School
January 1, 2008 - January 1, 2010
Master of Science in Electrical Engineering at National University of Sciences and Technology (NUST)
January 1, 2016 - September 1, 2018
Bachelor of Science in Electrical Engineering at University of Engineering and Technology (UET)
January 1, 2010 - June 1, 2014
High School Diploma (Edexcel GCE A Levels) at Saint Mary’s Catholic High School
January 1, 2008 - January 1, 2010

Qualifications

Cryogenics Safety Fundamentals
January 11, 2030 - January 8, 2026

Industry Experience

Computers & Electronics, Software & Internet, Education, Manufacturing, Professional Services