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I'm an interdisciplinary engineer and researcher with a strong foundation in electrical engineering and a growing focus on AI, NLP, and data-driven product development. I enjoy turning complex data and systems into practical ML models and robust hardware-software solutions, bridging the gap between research and real-world impact. I thrive in cross-disciplinary teams, contributing to public health projects, speech recognition pipelines, and hardware design. My curiosity drives me to explore new tools from PyTorch to Verilog, delivering solutions that combine rigorous experimentation with tangible outcomes.…I'm an interdisciplinary engineer and researcher with a strong foundation in electrical engineering and a growing focus on AI, NLP, and data-driven product development. I enjoy turning complex data and systems into practical ML models and robust hardware-software solutions, bridging the gap between research and real-world impact. I thrive in cross-disciplinary teams, contributing to public health projects, speech recognition pipelines, and hardware design. My curiosity drives me to explore new tools from PyTorch to Verilog, delivering solutions that combine rigorous experimentation with tangible outcomes.

PHUNG CHENG FEI

Data Scientist, AI Engineer, Data Analyst, +2

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I'm an interdisciplinary engineer and researcher with a strong foundation in electrical engineering and a growing focus on AI, NLP, and data-driven product development. I enjoy turning complex data and systems into practical ML models and robust hardware-software solutions, bridging the gap between research and real-world impact. I thrive in cross-disciplinary teams, contributing to public health projects, speech recognition pipelines, and hardware design. My curiosity drives me to explore new tools from PyTorch to Verilog, delivering solutions that combine rigorous experimentation with tangible outcomes.…I'm an interdisciplinary engineer and researcher with a strong foundation in electrical engineering and a growing focus on AI, NLP, and data-driven product development. I enjoy turning complex data and systems into practical ML models and robust hardware-software solutions, bridging the gap between research and real-world impact. I thrive in cross-disciplinary teams, contributing to public health projects, speech recognition pipelines, and hardware design. My curiosity drives me to explore new tools from PyTorch to Verilog, delivering solutions that combine rigorous experimentation with tangible outcomes.

Available to hire

I’m an interdisciplinary engineer and researcher with a strong foundation in electrical engineering and a growing focus on AI, NLP, and data-driven product development. I enjoy turning complex data and systems into practical ML models and robust hardware-software solutions, bridging the gap between research and real-world impact.

I thrive in cross-disciplinary teams, contributing to public health projects, speech recognition pipelines, and hardware design. My curiosity drives me to explore new tools from PyTorch to Verilog, delivering solutions that combine rigorous experimentation with tangible outcomes.

Skills

Experience Level

Expert

Expert

Expert

Expert

Intermediate

Intermediate

Intermediate

Intermediate

Intermediate

Language

English

Advanced

Work Experience

Engineer at TransPerfect

January 1, 2023 - October 18, 2025

Worked with client’s automated speech recognition and inference MLOps pipeline; cleaned up language data corpus datasets.

Research Associate at National University of Singapore (NUS)

January 1, 2023 - Present

Public health project on government COVID-19 vaccination and nationwide lockdown response; built NLP datasets and fine-tuned LoRA+SVD and LoRD NLP models (MAMBA, NLHF, diffusion LM).

Engineer at FTDI

January 1, 2022 - October 18, 2025

Investigated STA failure reports on USB3 FT600 chip; USB power-delivery v3.0; Verilog code; involved in FT4232HAN chip tapeout for synthesis, STA timing closure, TetraMax ATPG/scan Tcl scripts.

Engineer at ADECCO

January 1, 2021 - October 18, 2025

Synthesis Tcl for TSMC 6nm design with Cadence Genus, PBA/GBA, MCMM, DVFS, POCV flow; investigated re-timing algorithms and related flows.

Research Engineer at ADSC

January 1, 2020 - October 18, 2025

Implemented AXI memory controller for storing CNN parameters; analyzed Intel SGX binary for protection against attacks.

Research Associate at NTU (Nanyang Technological University)

January 1, 2019 - October 18, 2025

Modified both Verilog and C driver code for full-duplex capability from existing PCIe framework; implemented on Altera DE4 and Xilinx VC707.

Engineer at SHARP

January 1, 2016 - October 18, 2025

Designed, verified and bring-up PCBA; RF/IF schematics and layout; worked on high-speed signal lines such as HDMI, LVDS.