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I am a Bachelor of Engineering student in Computer and Communication Engineering at the American University of Beirut (AUB), with a strong focus on computer architecture and secure, integrity-driven systems. I have experience implementing an RV32I 5-stage pipelined RISC-V processor in Verilog, building a blockchain-based proof system for AI model integrity, and setting up ELK-based security monitoring and phishing simulation labs for cybersecurity learning.…I am a Bachelor of Engineering student in Computer and Communication Engineering at the American University of Beirut (AUB), with a strong focus on computer architecture and secure, integrity-driven systems. I have experience implementing an RV32I 5-stage pipelined RISC-V processor in Verilog, building a blockchain-based proof system for AI model integrity, and setting up ELK-based security monitoring and phishing simulation labs for cybersecurity learning.

Hussein Samer Kharroubi

Programmer, Blockchain Developer, Software Engineer, +2

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I am a Bachelor of Engineering student in Computer and Communication Engineering at the American University of Beirut (AUB), with a strong focus on computer architecture and secure, integrity-driven systems. I have experience implementing an RV32I 5-stage pipelined RISC-V processor in Verilog, building a blockchain-based proof system for AI model integrity, and setting up ELK-based security monitoring and phishing simulation labs for cybersecurity learning.…I am a Bachelor of Engineering student in Computer and Communication Engineering at the American University of Beirut (AUB), with a strong focus on computer architecture and secure, integrity-driven systems. I have experience implementing an RV32I 5-stage pipelined RISC-V processor in Verilog, building a blockchain-based proof system for AI model integrity, and setting up ELK-based security monitoring and phishing simulation labs for cybersecurity learning.

Available to hire

I am a Bachelor of Engineering student in Computer and Communication Engineering at the American University of Beirut (AUB), with a strong focus on computer architecture and secure, integrity-driven systems.

I have experience implementing an RV32I 5-stage pipelined RISC-V processor in Verilog, building a blockchain-based proof system for AI model integrity, and setting up ELK-based security monitoring and phishing simulation labs for cybersecurity learning.

Skills

Experience Level

Expert

Expert

Expert

Intermediate

Intermediate

Intermediate

Beginner

Beginner

Language

Arabic

Fluent

English

Advanced

Work Experience

Cybersecurity Intern (ELK Security Monitoring & Phishing Simulation Lab) at Touch – Cybersecurity Intern

July 1, 2026 - Present

Configured an ELK-based security monitoring environment using Elasticsearch, Logstash, Kibana, and Winlogbeat. Built and tested a phishing simulation lab with Kali Linux, GoPhish, Windows, and ELK to generate, collect, and analyze security events for incident monitoring demonstrations. Set up multi-node Elasticsearch clustering including networking, certificates, port configuration, and secure inter-node communication.

Cybersecurity Intern (ELK security monitoring & phishing lab) at Touch – Cybersecurity

July 1, 2026 - Present

Configured an ELK-based security monitoring environment using Elasticsearch, Logstash, Kibana, and Winlogbeat. Built and tested a phishing simulation lab using Kali Linux, GoPhish, Windows, and ELK to generate, collect, and analyze security events for incident monitoring demonstrations. Set up multi-node Elasticsearch clustering, including networking, certificates, ports, and secure node communication.

Cybersecurity Intern at Touch – Cybersecurity Intern (organization not specified)

July 1, 2026 - Present

Configured an ELK-based security monitoring environment using Elasticsearch, Logstash, Kibana, and Winlogbeat. Built and tested a phishing simulation lab using Kali Linux, GoPhish, Windows, and ELK to generate, collect, and analyze security events for incident monitoring demonstration. Set up multi-node Elasticsearch clustering, including networking, certificates, ports, and secure node communication.

Blockchain for AI Model Integrity (Web3/Ethereum) at Blockchain for AI Model Integrity

September 1, 2025 - December 31, 2025

Built a blockchain-based system in Python using Web3/Ethereum to verify AI model integrity by storing cryptographic hashes of model weights on-chain. Developed tools to detect model tampering via hash comparison. Authored an IEEE-formatted research paper describing the system and its security implications.

Blockchain for AI Model Integrity (Web3/Ethereum hash verification system)

September 1, 2025 - December 1, 2025

Built a blockchain-based system in Python (Web3/Ethereum) to verify AI model integrity by storing cryptographic hashes of model weights on-chain. Developed tools to detect model tampering through hash comparison. Authored an IEEE-formatted research paper describing the system and its security implications.

Blockchain for AI Model Integrity - Builder/Developer at Independent/Research Project

September 1, 2025 - December 1, 2025

Implementation of RISC-V Archer Processor (5-stage pipelined RV32I) at AUB - Extension of RISC-V Archer Processor

January 1, 2025 - Present

Implemented a 5-stage pipelined RV32I RISC-V processor in Verilog to replace a single-cycle baseline and improve instruction throughput. Designed hazard detection plus stalling, flushing, and forwarding logic to maintain correctness while keeping high pipeline utilization. Integrated instruction and data memory subsystems with byte-level access, immediate generation, branch handling, and ALU control. Created testbenches and validated functionality in Xilinx Vivado using custom RISC-V assembly and ROM models.

Extension of RISC-V Archer Processor (5-stage pipelined RV32I RV32I processor implementation) at AUB

January 1, 2025 - Present

Implemented a 5-stage pipelined RV32I RISC-V processor in Verilog, replacing a single-cycle baseline to improve instruction throughput. Designed hazard detection, stalling, flushing, and forwarding unit logic to maintain correctness while increasing pipeline utilization. Integrated instruction and data memory subsystems with byte-level access, immediate generation, branch handling, and ALU control. Created testbenches and validated functionality in Xilinx Vivado using custom RISC-V assembly and ROM models.

Extension of RISC-V Archer Processor - Implementer/Developer at AUB (Extension of RISC-V Archer Processor)

January 1, 2025 - Present

Implemented a 5-stage pipelined RV32I RISC-V processor in Verilog, replacing a single-cycle baseline to improve instruction throughput. Designed hazard detection with stalling, flushing, and forwarding to maintain correctness while maximizing pipeline utilization. Integrated instruction and data memory subsystems with byte-level access, immediate generation, branch handling, and ALU control. Created testbenches and validated functionality in Xilinx Vivado using custom RISC-V assembly and ROM models.