Jerrick Cuahutle

Led full product development from concept through manufacturing release, including requirements gathering, component selection, NPI, and design sign-off. Designed up to 30-layer RF and mixed-signal PCBs in Altium; built RF front-ends and antenna systems for GPS/GSM/LTE/5G/Wi-Fi/BLE/Zigbee/LoRa/UWB using HFSS/CST. Performed pre- and post-layout SI analysis (SIwave, Cadence Sigrity SystemSI), including S-parameter extraction, insertion/return loss, crosstalk, TDR impedance checks, and JEDEC/PCIe mask verification with IBIS-AMI. Closed Power Integrity using Cadence Sigrity (PowerDC/PowerSI) with DC IR-drop and AC impedance vs target-Z analysis on −48 VDC and multi-rail PDNs, including decoupling optimization and via current-density evaluation. Applied IPC standards and led DFM/DFT and NPI reviews with fabrication/assembly partners to reduce re-spins and address SI/PI/EMI/manufacturability findings from validation.

Architected board-level hardware for BLE/GSM and sensor-based IoT/AI systems. Designed and laid out high-speed, mixed-signal, and RF PCBs with controlled impedance, EMI-aware grounding, and HDI techniques. Conducted SI and RF antenna matching/tuning using ANSYS HFSS; validated board-level Power Integrity in Cadence Sigrity (DC IR drop, plane/via current density, and thermal co-simulation) for battery-powered and multi-rail designs prior to fabrication. Coordinated with fabricators and assembly houses on stack-ups, material choices, tolerances, panelization, and yield; also built fixture/interface boards for manufacturing validation and production screening. Designed power stages (switching regulators, LDOs, protection/charging circuits) with loop-area, ripple, and thermal considerations for reliable operation.

Served as principal engineer designing advanced PCB and hardware prototypes across IoT, RF communications, biomedical, and consumer products. Performed post-layout SI/PI/DC IR-drop analysis in ANSYS SIwave, Cadence Sigrity PowerSI, and HyperLynx, providing layout recommendations to close timing and impedance margins on high-speed nets. Extracted broadband S-parameter models of high-speed nets, via transitions, and package-to-board interfaces using HFSS/SIwave and correlated results against lab measurements (VNA/TDR). Delivered mil-grade and ruggedized designs aligned to customer requirements and MIL-STD environmental/EMC targets, applying Safety Integrity Levels and FMEA through design release, while maintaining SI/PI/EMI-aware layout practices.