Surya Naga Lakshmi Anjusha Khandavalli

Led the migration of Australian local services to a global supply chain management platform, implementing a unified system that streamlined operations across multiple HelloFresh markets. Served as the sole frontend developer for Claims Management and from repository setup through production launch, designing workflow architecture that dynamically determined UI states and notification requirements with strong market feedback. Built and deployed an Incident Management System integrating with Jira, maintaining complex data relationships while ensuring data integrity for supply chain disruption tracking. Developed features for HelloFresh (AU/NZ) Operations tools, including responsive interfaces for forecasting upcoming orders and performing operational tasks. Used NextJS, TypeScript, MUI, and Redux to build scalable internal solutions, and maintained ~80% test coverage using React Testing Library. Implemented end-to-end CI/CD workflows with GitHub Actions, including linting, unit/integrati

Executed end-to-end development of responsive web, mobile, and landing pages for one of the largest banking industry players, delivering consistent user experiences across platforms. Evolved from supporting tasks to contributing as a valuable member of the Solutions team, helping implement features such as deep linking, two-factor authentication, and upgrading functional capabilities. Worked on complex transaction flows supporting retail customer business features and UPI payment integrations. Improved troubleshooting and bug-fix capability by diagnosing and resolving performance bottlenecks and increasingly complex issues. Strengthened software quality practices by writing effective unit and UI tests. Built a travel aggregator application with Elixir, integrating multiple bus and train booking portals into a single portal.

Worked with x86 architecture and debugging tools, using makefiles, Linux commands, and PCIe concepts while performing bug reproduction in tool enhancements. Fixed validation issues and resolved seed integrity concerns for tool enhancements. Built understanding of random instruction generation for cache coherency and memory ordering validation in next-gen Intel processors. Contributed to GCC upgrade activities by transitioning from C98 to C11 and validating I/O (PCIe) support in non-standalone mode.