Validation Engineer at Intel

Performed post-silicon graphics memory failure analysis and debugging; conducted post-silicon system validation for client graphics memory; automated validation data collection and results post-processing through scripting; executed memory validation stress tests; performed post-silicon validation of the system to verify hardware/OS compatibility, software dependencies, performance and scalability requirements.

Lead Engineer at Intel

Redesigned SoC validation software tools in C and Python by porting them from Linux to Windows, enhancing compatibility and functionality; modified code to compile/run in Linux, WSL-Ubuntu, Cygwin, and Windows across multiple hardware boards; tested/debugged the tool across environments and CLI variants; designed/implemented a custom command line parser as a replacement for popt; embedded OpenCL code and configuration files into the tool executable for a self-contained solution; ported the Python component of the tool to C++, boosting performance and removing Python dependency.

Senior Software Engineer at Tveon

Developed a framework to study FFmpeg threading structure; benchmarked FFmpeg-based encoders for various video transcoding use cases; performed profiling with Linux Perf, VTune, and Gperftools on FFmpeg-based encoders across bare-metal, Docker containers, and Kubernetes clusters; benchmarked encoders in a batch processor as CI/CD jobs on a GitLab system; automated time-consuming benchmarking and logging scripts; documented multi-threaded application structure and results on Confluence.

Private Tutor at Self-Employed

Taught hardware design, computer architecture/organization, embedded systems, operating systems, systems programming, and programming (C/C++, Python, Assembly for ARM/RISC-V/x86, Bash); mentored/supervised hardware (RTL design, timing analysis, testbench, and verification) and software projects.

Research Assistant at University of Toronto

Created a framework to automatically identify the highest-performance algorithm from the algorithm space; designed algorithm description languages (Simplified C/ADL) and a Simplified C to ADL compiler in Python; developed timing models for N-core CPUs/GPUs and an ADL simulator using SystemC/C++.

R&D Senior Software Engineer at Pars Telephone Kar Co., Iran

Developed software in C for PABX operator consoles and call-processing traces; designed firmware for RTOS-based boards, the HDLC network, COM boards providing RS232 links with XMODEM, and test boards to automatically test line ports.

R&D Senior Hardware & Software Engineer at Chavosh Communication Co., Iran

Created hardware using FPGAs for PABX line interfaces and billing systems for 512-port PABXs; designed hardware/software for 512- and 16-port PABXs using Intel 80186/80188 and 8751 microcontroller.

R&D Hardware Engineer & Software Developer at Parstel Telecom. Co., Iran

Developed hardware/software for PC-based/stand-alone PABX operator consoles using Intel 8051 Assembly.

R&D Hardware Engineer at Iran Telecom. Research Center, Iran

Designed hardware/firmware for conference circuits, 1K/2K switches and E1 trunk interfaces using Intel 8086.

Lead Engineer at Intel

Redesigned SoC validation software tools in C and Python by porting them from Linux to Windows, enhancing compatibility and functionality. Modified the code to compile and run successfully in multiple environments (Linux, WSL-Ubuntu, Cygwin, and Windows) and on various hardware boards. Tested and debugged the tool to ensure functionality across various environments and with different CLI arguments. Designed and implemented a custom command line parser as a replacement for popt. Embedded OpenCL code and configuration files into the tool executable, creating a fully self-contained solution. Ported the Python component of the tool to C++, enhancing performance and making the tool independent of Python.

Senior Software Engineer at Tveon

Developed a framework to study FFmpeg threading structure. Benchmarked FFmpeg for various video transcoding use cases on different FFmpeg-based encoders. Conducted profiling using Linux Perf, VTune, and Gperftools on various FFmpeg-based encoders (bare-metal, Docker container, and Kubernetes clusters). Benchmarked FFmpeg-based encoders in a batch processor as CI/CD jobs on a GitLab system. Automated time-consuming benchmarking and logging scripts. Documented multi-threaded application structure, benchmarking and profiling results on Confluence pages.

Private Tutor at Self-Employed in Toronto

Taught hardware design, computer architecture/organization, embedded systems, operating systems, systems programming, and programming courses (C/C++, Python, Assembly (ARM/RISC-V/x86), and Bash). Mentored/supervised hardware (RTL design, timing analysis, testbench, and verification) and software projects.

Research Assistant at University of Toronto

Created a framework to automatically identify the highest-performance algorithm from the algorithm space. Designed algorithm description languages (Simplified C/ADL) and a Simplified C to ADL compiler in Python. Developed 1) timing models for N-core CPUs/GPUs and 2) an ADL simulator using SystemC/C++.

R&D Senior Software Engineer at Pars Telephone Kar Co.

Developed software in C for PABX operator consoles and call-processing traffic measurement. Designed firmware in C for an RTOS, the HDLC network for the system, COM boards with RS232 links and XMODEM, and test boards.

R&D Senior Hardware &Software Engineer at Chavosh Communication Co.

Created hardware using FPGAs for PABX line interfaces and billing systems for 512-port PABXs. Designed hardware/software for 512- and 16-port PABXs using Intel 80186/80188 and 8751 microcontroller.

R&D Hardware Engineer &Software Developer at Parstel Telecom. Co.

Developed hardware/software for PC-based/stand-alone PABX operator consoles.

R&D Hardware Engineer at Iran Telecom. Research Center

Designed hardware/ firmware for conference circuits, 1K/2K switches and E1 trunk interfaces using Intel 8086.