Intern (Thesis) at IMEC

Thesis project on developing a speech-to-text translation model based on State Space Models for neuromorphic hardware. The work includes distilling knowledge from transformer models into compact state-space representations, exploring activation sparsity with artificial neural networks and spiking neural networks, and optimizing hardware-aware execution on a RISC-V based neuromorphic platform.

Intern (Compiler Development) at IMEC

Internship - Developed a compiler for an event-driven, multi-core RISC-V based neuromorphic architecture optimized for neural networks using IREE, with custom HAL passes for tiling, multi-core splitting, and adapting to event-driven execution, lowering to LLVM IR.

Middleware Engineer at Intel Corporation

Contributed to a pipeline scheduler to offload computer vision workloads onto Intel VPU devices. Implemented in C++17, the scheduler integrated with the Intel VAAPI framework on the host and offloaded pipelines to VPU devices via PCIe. Designed with a client-server architecture, it supported both resource-based and round-robin scheduling for efficient workload distribution across VPU processing units. Also developed a Kubernetes-based device plugin to enable scheduling pipelines from a Kubernetes cluster and a Telegraf-based plugin to publish VPU resource utilization metrics.