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Hello! I'm Kyung Wook Park, a senior semiconductor leader with 30+ years of experience spanning IC design, DDR/SRAM memory development, mixed-signal integration, EDA/CAD verification, and design-to-mask preparation. I thrive on turning complex ideas into manufacturable silicon and data that tape out reliably with Tier-1 foundries across Europe and Asia. I partner with customers, foundries, and R&D teams to drive PDK development, process readiness, and successful tape-outs. Outside of work, I enjoy long-distance running, hiking, cycling, and studying European history. I believe in joyful living, frequent reflection, and giving thanks in all circumstances while balancing family and professional commitments.…Hello! I'm Kyung Wook Park, a senior semiconductor leader with 30+ years of experience spanning IC design, DDR/SRAM memory development, mixed-signal integration, EDA/CAD verification, and design-to-mask preparation. I thrive on turning complex ideas into manufacturable silicon and data that tape out reliably with Tier-1 foundries across Europe and Asia. I partner with customers, foundries, and R&D teams to drive PDK development, process readiness, and successful tape-outs. Outside of work, I enjoy long-distance running, hiking, cycling, and studying European history. I believe in joyful living, frequent reflection, and giving thanks in all circumstances while balancing family and professional commitments.

Kyung Wook Park

3D Designer, Product Designer, 3D Visualizer, +7

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Hello! I'm Kyung Wook Park, a senior semiconductor leader with 30+ years of experience spanning IC design, DDR/SRAM memory development, mixed-signal integration, EDA/CAD verification, and design-to-mask preparation. I thrive on turning complex ideas into manufacturable silicon and data that tape out reliably with Tier-1 foundries across Europe and Asia. I partner with customers, foundries, and R&D teams to drive PDK development, process readiness, and successful tape-outs. Outside of work, I enjoy long-distance running, hiking, cycling, and studying European history. I believe in joyful living, frequent reflection, and giving thanks in all circumstances while balancing family and professional commitments.…Hello! I'm Kyung Wook Park, a senior semiconductor leader with 30+ years of experience spanning IC design, DDR/SRAM memory development, mixed-signal integration, EDA/CAD verification, and design-to-mask preparation. I thrive on turning complex ideas into manufacturable silicon and data that tape out reliably with Tier-1 foundries across Europe and Asia. I partner with customers, foundries, and R&D teams to drive PDK development, process readiness, and successful tape-outs. Outside of work, I enjoy long-distance running, hiking, cycling, and studying European history. I believe in joyful living, frequent reflection, and giving thanks in all circumstances while balancing family and professional commitments.

Available to hire

Hello! I’m Kyung Wook Park, a senior semiconductor leader with 30+ years of experience spanning IC design, DDR/SRAM memory development, mixed-signal integration, EDA/CAD verification, and design-to-mask preparation. I thrive on turning complex ideas into manufacturable silicon and data that tape out reliably with Tier-1 foundries across Europe and Asia.

I partner with customers, foundries, and R&D teams to drive PDK development, process readiness, and successful tape-outs. Outside of work, I enjoy long-distance running, hiking, cycling, and studying European history. I believe in joyful living, frequent reflection, and giving thanks in all circumstances while balancing family and professional commitments.

Skills

Experience Level

Expert

Expert

Expert

Expert

Expert

Expert

Expert

Expert

Intermediate

Intermediate

Intermediate

Language

English

Fluent

Korean

Fluent

German

Advanced

Japanese

Beginner

Work Experience

Expert Design to Mask Preparation at Robert Bosch Semiconductor Manufacturing Dresden GmbH

April 1, 2025 - October 1, 2025

Tape-out activities and mask-data preparation for production (write-ready masks), including frame generation, multi-die placement, capturing, and resolution-enhancement techniques within scribe street. Leverage Mask Compose using Cadence Pegasus to create alignment/overlay markers, metrology targets, EM structure, CD-control features, and process-defect-monitoring cells using TSMC and TI processes; manage full mask data release. Perform Optical Proximity Correction and lithography to improve yield at the 300 mm wafer fab; programming scripts to streamline the design-to-mask flows. Lead the end-to-end process of adapting external TI and TSMC process technologies to Bosch’s internal manufacturing requirements, ensuring seamless integration into a highly automated fab environment.

Senior Customer Application Engineer, Physical Design and Verification at Siemens Electronic Design Automation (EDA) (formerly Mentor Graphics)

June 1, 2014 - March 1, 2025

Specialize in Calibre IC Physical implementation, ensuring efficient design verification and Design for Manufacturing (DFM) optimization for faster production and complete sign-off compliance. Provide on-site and online EU customer support; develop and debug customer software, address tool enhancement requests, and collaborate closely with R&D. Improve user experience by integrating feedback into application design and functionality for advanced nanometer silicon chip development. Conduct code reviews and debugging, driving best practices and enhancing overall code quality for customer PD/K teams. Deliver training on Programmable Electrical Rules Checking (PERC) and DFM Smart-FILL/ECO-FILL. Expertise in PERC, ESD/LUP, DFM methodologies, photonics devices DRC (non-rectangle, curvilinear). Proficient in coding and debugging in programming; familiar with advanced technologies across multiple foundries, LVS, ERC, Antenna, Parasitic Extraction, xACT, DESIGNrev, and TCL scripting.

Consultant / Customer Application Engineer at Mentor Graphics (now Siemens EDA)

June 1, 2014 - December 1, 2018

Dedicated to IC Manufacturing Backend, Calibre RET/OPC; Expertise in Resolution Enhancement Technology (RET) and Mask Data Preparation (MDP) for foundries. OPC simulation (ILT) and OPC-VERIFY; Sub-Resolution Assist Feature (SRAF), ModelFlow, Multi-Patterning, LithoView, Workbench, MPC (mask process correction) and Jobdeck. Developed manufacturable layouts for process development and yield improvement; collaborated with customers to ensure design-for-manufacturability.

Trainee German Language at CBZ München

December 1, 2013 - May 1, 2014

Completed German language training (Level B2) as part of new job orientation.

Consultant Sales Engineer Asia at DSP Weuffen GmbH

February 1, 2013 - November 1, 2013

Consulted to develop the automotive ADAS market; managed customer development in China and Korea; specialized in Digital Signal Processors with multi-camera, software/hardware, Ethernet, LVDS, surround-view, and traffic sign recognition technologies.

Consultant IC Design PDK Engineer at Infineon Technologies AG

December 1, 2012 - September 1, 2013

Wrote chip packaging design rules using Siemens Calibre for Wire-bond BGA, TSSOP and L-/T-/MQFP. Defined and released package DRC, created test cases, and qualified package designs. Acted as the interface between chip package offerings and OSAT partners Amkor, ASE Technology.

Senior Sales Manager Asia at ELMOS Semiconductor SE

January 1, 2010 - September 1, 2012

Managed distributors and regional sales operations; acted as sales representative between HQ and Asia-Pacific, ensuring alignment on strategy and execution. Supported ASIC development projects.

Trainee German Language Course at Goethe Institute

August 1, 2009 - December 1, 2009

Completed German language course (Goethe).

Senior IC Physical Designer at Qimonda AG / Infineon Technologies

September 1, 2004 - July 1, 2009

Physical design for DRAM DDR1 memory and analog/mixed-signal circuits; LVS/DRC; floor planning; ESD; IR-drop; EM analysis; tape-outs and sign-off; contributed to 45nm CMOS process capability; memory solutions.

Senior IC Design Engineer at Integrated Silicon Solution Inc.

January 1, 2004 - July 1, 2004

Led physical design for 256Mb Low Power SDRAM; authored Hercules DRC/LVS rule decks; mask revision; RTL-to-GDS flows; P&R; processed with packaging collaborations.

Senior IC Design Engineer at SK-Hynix Semiconductor

February 1, 1996 - December 1, 2003

Designed and simulated core and peripheral circuits (decoders, PLL, I/O drivers, ESD/LUP, sense amplifiers, Refresh, state machines, voltage regulators); defined DDR1 specifications; led full-chip physical IC design for SDRAM and DDR1 cores; automation flow development and mask data preparation.