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Hello! I'm Kyung Wook Park, a senior semiconductor leader with 30+ years of experience spanning IC design, DDR/SRAM memory development, mixed-signal integration, EDA/CAD verification, and design-to-mask preparation.
Hello! I’m Kyung Wook Park, a senior semiconductor leader with 30+ years of experience spanning IC design, DDR/SRAM memory development, mixed-signal integration, EDA/CAD verification, and design-to-mask preparation. I thrive on turning complex ideas into manufacturable silicon and data that tape out reliably with Tier-1 foundries across Europe and Asia.
I partner with customers, foundries, and R&D teams to drive PDK development, process readiness, and successful tape-outs. Outside of work, I enjoy long-distance running, hiking, cycling, and studying European history. I believe in joyful living, frequent reflection, and giving thanks in all circumstances while balancing family and professional commitments.
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Tape-out activities and mask-data preparation for production (write-ready masks), including frame generation, multi-die placement, capturing, and resolution-enhancement techniques within scribe street. Leverage Mask Compose using Cadence Pegasus to create alignment/overlay markers, metrology targets, EM structure, CD-control features, and process-defect-monitoring cells using TSMC and TI processes; manage full mask data release. Perform Optical Proximity Correction and lithography to improve yield at the 300 mm wafer fab; programming scripts to streamline the design-to-mask flows. Lead the end-to-end process of adapting external TI and TSMC process technologies to Bosch’s internal manufacturing requirements, ensuring seamless integration into a highly automated fab environment.
Dedicated to IC Manufacturing Backend, Calibre RET/OPC; Expertise in Resolution Enhancement Technology (RET) and Mask Data Preparation (MDP) for foundries. OPC simulation (ILT) and OPC-VERIFY; Sub-Resolution Assist Feature (SRAF), ModelFlow, Multi-Patterning, LithoView, Workbench, MPC (mask process correction) and Jobdeck. Developed manufacturable layouts for process development and yield improvement; collaborated with customers to ensure design-for-manufacturability.
Specialize in Calibre IC Physical implementation, ensuring efficient design verification and Design for Manufacturing (DFM) optimization for faster production and complete sign-off compliance. Provide on-site and online EU customer support; develop and debug customer software, address tool enhancement requests, and collaborate closely with R&D. Improve user experience by integrating feedback into application design and functionality for advanced nanometer silicon chip development. Conduct code reviews and debugging, driving best practices and enhancing overall code quality for customer PD/K teams. Deliver training on Programmable Electrical Rules Checking (PERC) and DFM Smart-FILL/ECO-FILL. Expertise in PERC, ESD/LUP, DFM methodologies, photonics devices DRC (non-rectangle, curvilinear). Proficient in coding and debugging in programming; familiar with advanced technologies across multiple foundries, LVS, ERC, Antenna, Parasitic Extraction, xACT, DESIGNrev, and TCL scripting.
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