I am an analog circuit designer with more than 10 years of experience. I have completed several projects ranging from designing PCBs to taping out multiple integrated circuits. I have experience in PCB design tools, RTL programming, FPGA programming and Cadence virtuoso tools.

Kapil Kesarwani

I am an analog circuit designer with more than 10 years of experience. I have completed several projects ranging from designing PCBs to taping out multiple integrated circuits. I have experience in PCB design tools, RTL programming, FPGA programming and Cadence virtuoso tools.

Available to hire

I am an analog circuit designer with more than 10 years of experience. I have completed several projects ranging from designing PCBs to taping out multiple integrated circuits. I have experience in PCB design tools, RTL programming, FPGA programming and Cadence virtuoso tools.

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Experience Level

Language

English
Advanced

Work Experience

Analog Design Engineer at Texas Instruments
January 1, 2022 - Present
Design / lead analog circuits design, gate drivers, power stage and current sense amplifier design for point of load buck converter applications including servers, comms, industrial and automotive.
Principal Power IC Design Engineer at ETA Wireless (acquired by Murata Electronics NA)
January 1, 2020 - January 1, 2022
Power IC Architect and lead designer for the power-management IP based on integrated switched capacitor converter and buck-boost converter.
Senior Power IC Design Engineer at Allegro Microsystems LLC
January 1, 2015 - January 1, 2020
Power IC architect for automotive grade DC-DC converters with digital voltage mode control. Extremely low duty ratio converters targeting 40 V to 2.5 V down conversion. High frequency (2 MHz) DC-DC converters for the upcoming 48 V automotive rail for mild hybrids and electric vehicles. Designed integrated circuit blocks such as amplifiers, comparators, bandgap circuits, oscillators, DC/DC converters, and switched capacitors.
Graduate Research Assistant at Thayer School of Engineering at Dartmouth
January 1, 2011 - January 1, 2015
Project Abstract: Increasing power levels across a range of applications require high density high efficiency power converters. Aggressively scaling of switching frequency leads to power converters with high density but with moderate efficiency. My thesis explored resonant and multi-mode operation of inductive Switched Capacitor power converters for high density high efficiency power conversion. It was shown that multi-mode operation of ReSC converters merges the soft charging and resonant mode of operation of a general SC topology merged with an inductor. FCML converters were also explored for their architectural advantages as a promising inductive SC topology.
Senior Design Engineer - Power Management Group at Solar Semiconductor
January 1, 2010 - January 1, 2011
Worked on resonant switched capacitor topology for solar panel integrated power electronics products that boost the efficiency of a solar panel installation by 5-30%. Developed prototypes for a data monitoring product for remote monitoring of solar installation.
Design Engineer - Silicon Validation at Cosmic Circuits
January 1, 2007 - January 1, 2010
Team lead for Analog -Front -End (AFE) validation team. Designed and developed a complete validation platform for full validation of AFE IP’s. The full validation platform consists of customised instrumentation, high speed data capture cards and proprietary LabVIEW and FPGA software. This platform reduces design cycle time drastically.
Graduate Technical Intern at Maxim Integrated
June 1, 2013 - August 31, 2013
Develop control strategy for achieving high control bandwidth in a multi-phase buck converter.
Intern at Cosmic Circuits
June 1, 2006 - August 31, 2006
Developed digital architecture for a high-speed FPGA based board that could be used on several automated platforms that collect critical performance data on various IP’s developed by Cosmic Circuits.

Education

PhD in Power Electronics and Integrated Circuit Design at Thayer School of Engineering at Dartmouth
January 1, 2011 - January 1, 2015
B Tech + M Tech in Microelectronics and VLSI at Indian Institute of Technology (I.I.T) Chennai
January 1, 2002 - January 1, 2007

Qualifications

IEEE COMPEL Best Paper Award
January 1, 2013 - January 8, 2026
IEEE APEC Best Presentation Award
January 1, 2015 - January 8, 2026
IEEE COMPEL Travel Grant Award
January 1, 2012 - January 8, 2026
IEEE COMPEL Travel Grant Award
January 1, 2014 - January 8, 2026
IEEE APEC Travel Grant Award
January 1, 2015 - January 8, 2026
ARPA-E Innovation Summit Travel Grant Award
January 1, 2012 - January 8, 2026
ARPA-E Innovation Summit Travel Grant Award
January 1, 2014 - January 8, 2026
ARPA-E Innovation Summit Travel Grant Award
January 1, 2015 - January 8, 2026

Industry Experience

Computers & Electronics, Manufacturing, Software & Internet, Professional Services, Energy & Utilities