Available to hire
I’m Fan Hu, a Senior Software & Research Engineer with over 10 years of experience building distributed AI systems, GPU-accelerated computing, and compiler optimisation. I specialise in C/C++, Python, and CUDA, delivering scalable AI and data platforms for finance, education, and transportation, and I enjoy translating research ideas into production-ready, high-performance solutions.
I have led end-to-end projects across on-premise and cloud environments, implemented MLIR/LLVM-based optimisations, and integrated AI accelerators with OpenStack and Kubernetes. I thrive on structured delivery methods and cross-functional collaboration, balancing rapid prototyping with lifecycle validation to ensure robust, scalable systems used by thousands of users.
Experience Level
Expert
Expert
Expert
Expert
Expert
Expert
Expert
Expert
Expert
Expert
Expert
Intermediate
Intermediate
Intermediate
Language
English
Advanced
Chinese
Fluent
Work Experience
Senior AI Systems Engineer / Architect at Enflame Technology
April 1, 2021 - PresentEnd-to-end performance and reliability across accelerator stacks for LLM inference and model training at data-centre scale. Led cross-team hardening, resolved PCIe link training and card-drop, BMC access, thermal and power-mode issues, and authored runbooks for operations. Optimized the LLM inference path (prefill/decoder, KV cache, token pipeline, post-processing) to improve tokens/sec and tail latency. Contributed to compiler/runtime fusion and tiling passes; delivered x86/ARM bring-up and maintained ABI/SIMD-aware paths for heterogeneous servers. Led POCs with cloud/enterprise clients and produced performance reports and handover documentation.
Principal Applications Engineer at PMC – Sierra (later Microchip)
January 1, 2021 - October 15, 2025Owned board bring-up and reference designs for high-speed SerDes/OTN demo platforms; collaborated with silicon, firmware and customer teams to resolve interoperability and stability issues. Built test harnesses and validation workflows; supported customer integrations from early prototype to production deployment. Produced design notes and application guides consumed by internal teams and external partners.
Software Engineer / Feature Owner at Nokia Siemens Networks R&D
January 1, 2012 - October 15, 2025Developed and maintained Linux drivers/modules for telecom systems; coordinated feature delivery across multi-vendor chipsets (FPGA/ASIC). Improved reliability and observability on operator-grade platforms; supported field issues with structured RCA.
Software Engineer at BDCOM
January 1, 2009 - October 15, 2025Worked on Ethernet/switch-related drivers and platform integration; contributed to device bring-up and system stability.
Staff Researcher at Enflame Technology
April 1, 2021 - PresentDeveloped a distributed parallel computing compiler for AI/HPC workloads, supporting collective communication operators and aligning with GPU/DSA micro-architecture design. Implemented and optimised deep-learning and numerical operators (Softmax, Attention, BatchNorm, Top-K) through tiling, algorithm fusion, and memory-access optimisation. Built MLIR and LLVM optimisation passes for operator fusion, loop transformation, and memory-layout optimisation to enhance compiler performance. Conducted performance profiling and debugging across simulation (C-Model, VDK), FPGA (Zebu), and GPU clusters using event counters and PCIe protocol analysis. Performed system-level optimisation of AI solutions, tuning Redis throughput and GPU efficiency in computer-vision pipelines via decoder-card and server-configuration analysis. Leveraged KTransformer to offload part of large-language-model computation from GPU, improving system-level scalability for distributed training. Contributed to academic public
Principal Application Engineer at PMC – Sierra (later Microchip)
December 31, 2021 - October 17, 2025Owned board bring-up and reference designs for high-speed SerDes/OTN demo platforms; collaborated with silicon, firmware and customer teams to resolve interoperability and stability issues. Built test harnesses and validation workflows; supported customer integrations from early prototype to production deployment. Produced design notes and application guides consumed by internal teams and external partners.
Software Engineer / Feature Owner at Nokia Siemens Networks R&D
December 31, 2012 - October 17, 2025Developed and maintained Linux drivers/modules for telecom systems; coordinated feature delivery across multi-vendor chipsets (FPGA/ASIC). Improved reliability and observability on operator-grade platforms; supported field issues with structured RCA.
Software Engineer at BDCOM
December 31, 2009 - October 17, 2025Worked on Ethernet/switch-related drivers and platform integration; contributed to device bring-up and system stability.
Staff Researcher at Enflame Technology
April 1, 2021 - October 31, 2025Led development of a domain-specific language compiler front-end for distributed AI/HPC workloads; designed LLVM/MLIR optimisation passes; managed on-premise AI/HPC cluster lifecycle with Slurm, Ansible, and Prometheus/Grafana; integrated heterogeneous accelerators via OpenStack Cyborg; delivered AI solutions across education, finance, and transportation; built an on-prem LLM-based retrieval system and real-time monitoring; optimized core operators; offloaded LLM compute with KTransformer, boosting throughput.
Principal Application Engineer at PMC – Sierra (later Microchip)
December 31, 2021 - December 31, 2021Led board bring-up and reference design for high-speed SerDes and optical transport; delivered turnkey solutions to Tier-1 and Tier-2 customers worldwide; conducted post-silicon validation across three chip generations; built GUI and automation for automated testing; developed IoT-enabled apps and AWS-based lab integration; authored customer-facing reference solutions and technical guides.
Software Engineer / Feature Owner at Nokia Siemens Networks R&D
December 31, 2012 - December 31, 2012Developed Linux kernel drivers and C/C++ modules for telecom systems; led feature group for 1.0 release under FDDP; contributed to Shanghai World Expo 2010 Finland Pavilion demo showcasing optical/Ethernet switching; coordinated multi-vendor debugging; improved observability and maintainability via RCA and driver optimization.
Software Engineer at BDCOM
December 31, 2009 - December 31, 2009Worked on Ethernet switch/router drivers and platform integration; contributed to device bring-up and system stability.
Principal Application Engineer at PMC – Sierra (later Microchip)
January 1, 2012 - December 31, 2021Led board bring-up, validation, and reference design for high-speed SerDes and optical transport demo platforms; delivered turnkey solutions for six Tier-1 and four Tier-2 telecom and datacom customers across China, Japan, South Korea, North America, India, and Europe. Executed progressive post-silicon validation across three generations of communication chips: 1st-gen 100G — automated GUI-based configuration and remote instrument control; 2nd-gen 2×100G — Python/Pytest regression improving coverage and turnaround; 3rd-gen 400G — C++/Qt/SQL/RabbitMQ/TypeScript/Android apps with AWS-based RabbitMQ integration to link distributed test instruments with lab infrastructure, enabling remote monitoring of subsystem interoperability and performance. Built automated test harnesses and CI pipelines; collaborated with silicon, FPGA, and software teams to debug PCIe, I2C, SPI, and MDIO; contributed to joint reference solutions and customer demonstrations.
Software Engineer / Feature Owner at Nokia Siemens Networks R&D
January 1, 2009 - December 31, 2012Developed and maintained Linux kernel drivers and C/C++ modules for telecom systems, enabling communication between control and switching cards and supporting MIB-based management interfaces. Led the feature group for the 1.0 release under the FDDP development framework; delivered the Shanghai World Expo 2010 Finland Pavilion demo prototype showcasing next-generation optical and Ethernet switching technologies. Oversaw hardware selection for service boards, resolved critical customer issues for Deutsche Telekom and KDDI, and coordinated debugging across multi-vendor chipsets; improved observability and maintainability across subsystems.
Software Engineer at BDCOM
January 1, 2008 - December 31, 2009Worked on Ethernet switch/router drivers and platform integration; contributed to device bring-up and system stability.
Education
Master of Engineering Management at Shanghai Jiao Tong University
January 1, 2023 - January 1, 2025Bachelor of Electronic Science & Technology at Nanjing University
January 1, 2004 - January 1, 2008Master of Engineering Management at Shanghai Jiao Tong University
January 1, 2023 - January 1, 2025Bachelor of Electronic Science & Technology at Nanjing University
January 1, 2004 - January 1, 2008Master of Engineering Management at Shanghai Jiao Tong University
January 1, 2023 - January 1, 2025Bachelor of Electronic Science & Technology at Nanjing University
January 1, 2004 - January 1, 2008Master of Engineering Management at Shanghai Jiao Tong University
January 1, 2023 - January 1, 2025Bachelor of Electronic Science & Technology at Nanjing University
January 1, 2004 - January 1, 2008Qualifications
Data Processor (DPU) — Part 1: Reference Framework (T/CESA 1305.1-2024)
January 1, 2024 - October 15, 2025DPU Performance Testing — Part 1: Test Framework (T/CESA 1306.1-2024)
January 1, 2024 - October 15, 2025DPU Performance Testing — Part 2: Virtual Switch Acceleration (T/CESA 1306.2-2024)
January 1, 2024 - October 15, 2025DPU — Part 1: Reference Framework (T/CESA 1305.1-2024)
January 1, 2024 - October 17, 2025DPU Performance Testing — Part 1: Test Framework (T/CESA 1306.1-2024)
January 1, 2024 - October 17, 2025DPU Performance Testing — Part 2: Virtual Switch Acceleration (T/CESA 1306.2-2024)
January 1, 2024 - October 17, 2025AWS Certified Solutions Architect – Professional
January 11, 2030 - October 31, 2025Passed CFA exams
January 11, 2030 - October 31, 2025DPU standards (T/CESA 1305.1-2024) — Data Processor reference framework
January 1, 2024 - October 31, 2025DPU Performance Testing — Part 1: Test Framework (T/CESA 1306.1-2024)
January 1, 2024 - October 31, 2025DPU Performance Testing — Part 2: Virtual Switch Acceleration (T/CESA 1306.2-2024)
January 1, 2024 - October 31, 2025AWS Certified Solutions Architect – Professional
January 11, 2030 - December 3, 2025CFA Exams (Passed all levels)
January 11, 2030 - December 3, 2025Industry Experience
Computers & Electronics, Software & Internet, Telecommunications, Professional Services, Media & Entertainment, Financial Services, Education, Transportation & Logistics
Experience Level
Expert
Expert
Expert
Expert
Expert
Expert
Expert
Expert
Expert
Expert
Expert
Intermediate
Intermediate
Intermediate
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